Nowadays, various semiconductor devices such as semiconductor integrated circuits (ICs) are manufactured as independent semiconductor parts. These semiconductor devices are used in various kinds of electronic apparatuses. Such semiconductor device has a chip including semiconductor ICs (the chip hereinafter referred to as IC chip body) packaged in such a way that the ICs can be connected to external devices via external terminals provided on the device.
The IC chip body is provided with many electrode pads (hereinafter simply referred to as IC pads). Each of the pads is connected to an associated external terminal. In recent years, however, a method of connecting the pads to the external terminals has been increasingly changed from conventional one that utilizes flat-pack type QFP (Quad Flat Package) or SOP (Small Outline Package) that utilizes lead terminals, to one that utilizes a ball grid array (BGA) structure.
A chip-size package (CSP) has been also in use that is based on a similar connection technique utilizing BGA. The CSP has substantially the same outside dimensions as the IC chip body used. In a CSP structure, pads are provided on one side of a substrate for use in packaging the ICs (hereinafter referred to as package substrate), each pad facing an associated pad of the IC chip body. Provided on the other side of the package substrate are ball-shaped external electrodes arranged in a two-dimensional lattice (or grid). The pads are respectively connected to associated external electrodes on the package substrate (See, for example, Japanese Patent Early Publication No. H10-50922).
Each of the external electrodes of the CSP has a ball-shaped solder bump and arranged in a two-dimension array over a predetermined area of the underside of the semiconductor device. Thus, the CSP can be formed thin and compact in size close to the size of the chip. Further, the CSP can be mounted on the surface of a printed-circuit board.
In a semiconductor device having a conventional QFP structure, the external electrodes are arranged at substantially the same locations as the pads of the IC chip body. Therefore, if a signal line that is likely to interfere with other signal lines exists, the interference can be reduced by simply laying out the IC pads not to incur such interference.
In a semiconductor device having a grid array structure, many external electrodes are arranged in a two-dimension lattice. In this case also, if signal lines exist that are likely to incur interference with other signal lines when located in close proximity, pads for these signal lines are separated and spaced apart from one another, thereby suppressing possible interference. However, under a certain layout of numerous external electrodes in a two-dimensional lattice of on a package substrate, a case may arise where some of the external electrodes can come in close proximity to one another, though the IC pads connected to these external electrodes are separated and spaced apart. As a consequence, a problem arises then that signal lines that can interfere when located in close proximity are actually come in close proximity.